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Our Services

Design For Testability

Design For Testability

Test plan/DFT Architecture and DFX methodology development.

JTAG planning and implementation for AC and DC.

Scan insertion: Scan chain generation.

Test pin optimization for less IOs.

ATPG, Test pattern verification, simulation.

MBIST insertion: Controller logic and optimization.

Silicon Bringup, wafer sort ,package test and Production Program optimization support for tester

Formal Verification/equivalence check at each stage of design.

DFT mode STA constraint generation and verification.

AMS IP testing and Verification from parametric testing point of view.

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