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Design Functional Verification
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Design Functional Verification
Verification IP (VIP) : VIP development, customization and verification.
IP Design Verification : Build testbench from scratch, Enhance legacy testbench, Port testbench acros smethodology and verify same with self checking mechanism.
Subsystem Verification : Integrate IPs and Glue logic ,Develop Testbench re-using IP level Testbench infrastructure as much as possible, Ensure Connectivity, Functionality, Performance.
SOC level verification : Develop C-SV based Testbench in UVM/OVM ,Ensure Connectivity, Functionality, Performance, Develop use case scenarios
Domain Specific Service key notes
Verify the functionality w.r.t different FPGA.
Ensure all the artefacts are compliance with DO-254 avionics standard.
Development of the verification environment as per the avionics standard coding guideline.
All implementation are inline with agile review process to make sure there is no process violation.
Take the complete ownership of the verification issues that have been raised, do follow up with the designers to have a close on the issues.
