Physical Design Training
Physical Design : Basics
What is Physical Design?
The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them.
In other words, Physical design is the process of turning a design into manufacturable geometries.
According to Moore’s Law, transistor density on a microchip doubles every 18 months. Number of components increase and size of the chip is decreasing so system complexity increases at every step of the physical design process cycle.
Different steps of Physical Design process cycle
Floor Plan
Floor Plan is the first major step in getting your layout done. Your Floor Plan determines your chip quality.
Power Plan
Power plan contains designing of power distribution network with minimum static & dynamic IR drop.
Placement
Placement is the process of arranging all the functional standard cells in the core region with the consideration of performance, power, routability and total wire length.
Clock Tree Synthesis
Clock tree synthesis (CTS) is a process of distributing clock to each & every sequential element with minimum skew. CTS determine the performance of your chip in terms of power & timing.
Routing
Routing is the process of creating physical connections based on logical connectivity and it must be timing & physical DRC aware.
Advanced Modules of Physical Design
Module 0
Basics refresh and practical application of same
Basics of voltage, current, resistor capacitor
Digital Design Concepts and Verilog basics
CMOS Family design concepts
Introduction to Unix and gvim, details of commands
Introduction to scripting with PERL/Tcl
Introduction to ASIC Flow and chip fabrication
Module 1
Basics of Synthesis and Physical Design
Basic steps of synthesis: translation, optimization & technology mapping Understanding of timing constraints during synthesis.
What is Physical Design?
Lower node challenges & impact on Physical Design.
Physical Design importance in ASICs
Physical Design flow
Overview of different steps of Physical Design process cycle
Module 2
Floorplan, Power plan, Placement, CTS & Route - Complete PnR cycle
Floorplan
Power plan
Placement
Clock-Tree-Synthesis and skew balancing
Routing
Understanding various parameters (quality) for each of the steps
Module 3
Static Timing Analysis
Importance of STA over DTA
Delay Calculation
Maximum frequency calculation
Skew and Jitter
Setup & hold checks, analysis & timing closure techniques.
Design rule violations (DRV) and other checks.
Module 4
Physical Verification and other sign-off checks
Design rule check (DRC)
Layout vs Schematic check (LVS)
Antenna check, Electrical rule checks (ERC)
Design for manufacturability (DFM)
Logical equivalence check (LEC)
Module 5
Low Power Design Implementation
What is low power design?
Requirement of low power design.
Basic & advanced concepts of low power design
Module 6
Exposure to PNR Industry
Expert sessions from Industry experts
Brief on soft skills development - Semiconductor specific
Resume preparation
Mock interviews
Recent trends and ongoing PNR flows in known semiconductor companies