Design For Testability Training
Design For Testability : Basics
Importance of Testing
According to Moore’s Law, Number of Transistors on a microchip doubles every 18 months. Number of components increase and size of the chip is Decreasing so system complexity increases.
The reduction in feature size increases the probability that a manufacturing defect in the IC will result in a faulty chip.
Have there been problems during production?
Does the circuit contain faults?
Testing is required to guarantee fault-free chips.
Why & What is DFT?
Post Production testing is necessary because the process of manufacturing is not 100% error free.
DFT is a technique, which facilitates a design to become testable after production. It verifies the actual correctness of manufactured Hardware and extra logic which we implement in the design, which helps post-production structural testing.
Testing is for manufacturing flaws, not to check Functionality!!
Help to increase controllability and observability.
Controllability : Be able to force known values from primary inputs.
Observability : Be able to observe known values from the primary outputs.
Advanced Modules of Physical Design
Module 1
DFT Basics
What is DFT?
Why we do DFT?
Advantage /Disadvantages
Test process and where DFT comes in ASIC Design flow
Structural testing
Physical defect(Detail study on all defects as well as how defect converts to fault)
Fault modeling. Types of fault in detail. Detail study on all fault models.
Types of scan flops. There detail study with all pros/cons
Types of scan. There detail study.
Test point insertion.
Explain one practical model that gives idea on shifting ,launch and capturing on flops
Module 2
Scan Insertion
Different Scan styles
a. Mux-D scan flip flop
b. Clocked scan
c. LSSD (Level sensitive scan design)
Scan chain operation
Scan and timing constraints understanding
Scan insertion methodologies
Detail knowledge of each step in scan insertion flow.
Top down/ Bottom up approach
Full scan/Partial scan
Test point
Library content
Output file understanding
Major DRC that need to be checked.
General flow to solve any DRC.
Auto fix
Insertion flow with synopsis DFT Compiler
Module 3
ATPG
Overview of ATPG. Why we required?
Input files and its details.
Library and netlist formats.
Controllability & Observability overview
ATPG process flow.
Detail study of SPF file.
Different Fault models and there processes to generate patterns. Along with all the aspects that are used to generate particular pattern.
Test coverage & Fault coverage
Fault categories with details.
Major DRC to focus on and flow to solve any particular DRC.
Flow to analyze coverage. Which fault category we target first?
Fault collapsing and equivalence with example.
What is compression? Why we do that. example.
Compression structure of various vendors.
Module 4
Pattern validation
What is pattern validation?
What is GLS?
Types of pattern and format.
Setup file for environment setup
Inputs/outputs
How to give input pattern file
Tools that are used to do pattern validation
Tools used to debug failures.
How to debug pattern failure.
Timing simulation w.r.t. PVT corners
Basics of STA
Diagnosing pattern
How to debug compressed pattern.
ATE basics.
Module 5
JTAG
Need for Boundary scan
Structure of JTAG and required pins.
FSM for JTAG.
Tap controller. Understanding of all the states.
Detail understanding on all JTAG Instruction(Mandatory as well as User defined)
Boundary scan definition
Boundary scan Architecture
Types of Boundary scan cell
Structure of BSR.
BSDL
List all the tools that are used for JTAG insertion.
Module 6
MBIST
Basic memory model
Memory test techniques
Ram functional fault models.
Functional testing
Memory boundary scan
Multiplexer isolation
Built in self-test with its implementation
Memory Test algorithms
Memory faults models
MBIST architecture
List all the tools that are used to do MBIST
Module 7
IEEE 1500
Overview of ATPG. Why we required?
Requirement of IEEE 1500.
Input/output pins.
Basic Principles
Overall Architecture
Core Test Requirement / Architecture
Instruction set
Wrapper Register Function / Configuration
Wrapper Cells
Module 8
Scripting
Perl, Shell and TCL
Scenario will be given. Creating script for the same.
Module 9
Static Timing Analysis
Importance of STA over DTA.
Delay Calculation
Maximum frequency calculation
Skew and Jitter
Setup & hold checks, analysis & timing closure techniques
Design rule violations (DRV) and other checks.